The subject matter disclosed herein relates to solutions for integrating manufacturing feedback into integrated circuit structure designs. More specifically, aspects of the invention provide for improving the timing closure of a subsequent integrated circuit design by using manufacturing feedback (e.g., parameter settings and a regression analysis) from an initial integrated circuit design.
Modern integrated circuits (ICs) exhibit large amounts of variability in their performance, due in part, to variations in manufacturing processes and environmental parameters. The ranges of these variations defines a process space, and at differing points in the process space differing timing paths may be critical. Static timing analysis (STA) is one approach used to analyze, debug, and validate the time performance of an integrated circuit chip during the design phase and in advance of actual fabrication. The timing of the chip is simulated to determine if it meets the timing constraints to achieve timing closure and, therefore, is likely to operate properly if fabricated in accordance with the tested design.
A conventional method for determining the performance of circuitry on an integrated circuit chip (e.g., an application specific integrated circuit, or ASIC chip), after fabrication of the wafer, is through the use of a Performance Scan-Ring Oscillator (PSRO), or PSRO circuit. A PSRO circuit acts as a free-running ring of memory elements passing a pulse, the output of which can be measured at a reserved chip output pin. “Free-running” implies a circuit that is not clocked externally, and will run as fast as the signals can propagate through the logic of the circuit, i.e., limited only by the capabilities of the technology and manufacturing process variations. The periodicity of the PSRO circuit output provides a relative indication of the circuit speed, i.e., short period means faster circuit speed. PSROs are used to gauge the quality of the fabrication process, determine the speed of the circuitry on various parts of the wafer, and thereby grade the performance of individual chips on the wafer, before and after dicing. There may be more than one PSRO on a large ASIC in order to account for process variation within the chip.
However, the PSRO approach has some general shortcomings. For example, the PSRO approach leads to developing required coverage constraints that are larger than necessary to form the desired chip feature. In particular, the PSRO approach may be insufficient in the worst-corner (WC) timing limit scenario. A corner refers to a set of process parameters/environmental conditions (or simply, parameters) that cause variations in the static timing analysis of an integrated circuit. Corners may include, for example, a “best case” corner that provides the fastest path delay between two particular nodes in a circuit path, or “worst case” corner that provides the slowest path delay between two particular nodes in a circuit path. Where the worst-corner (WC) or worst-case timing limit is concerned, the conventional PSRO approach may lead to an inaccurate WC timing limit due to the larger-than necessary required coverage constraints.